Weekend VLSI

Module : `timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// // Company: Weekendvlsi.blogspot.com // Engineer: Weekendvlsi // Create Date:  // Design Name: Rational clock divider - Division by 4.5  // Module Name:  clk_div // Project Name:  // Target Devices:  // Tool Versions:  // Description:  // Dependencies:  // Revision: // Revision 0.01 - File Created // Additional Comments: //  ////////////////////////////////////////////////////////////////////////////////// module clk_div (clk,rst,clk_4_5);   input clk; input rst; output clk_4_5;   reg [8:0]  count;   reg  SATcount1,SATcount5,SATcount6 ;    /* Counter rst value : 9?b000000001 */ /* count is a  ring counter */   always @( posedge clk or posedge rst) if (rst) count <='d1; else begin count <= count << 1; count[0] <= count[8]; end always @(negedge clk or posedge rst) ...

8x8 Vedic Multiplier using Ripple carry adder and 4x4 multiplier module vedic8x8( input [7:0] a,b,  output [15:0] prod ); wire [7:0] mult0, mult1, mult2, mult3; wire [7:0] sum0; wire [11:0] sum1, sum2; wire carry0, carry2, carry3; vedic4x4 VM_i0(a[3:0],b[3:0],mult0); vedic4x4 VM_i1(a[3:0],b[7:4],mult1); vedic4x4 VM_i2(a[7:4],b[3:0],mult2); vedic4x4 VM_i3(a[7:4],b[7:4],mult3); ripple_adder_8bit RA_i0({4'b0,mult0[7:4]},mult2,1'b0,sum0,carry0); ripple_adder_12bit RA_i1({4'b0,mult1},{mult3,4'b0},1'b0,sum1,carry1); ripple_adder_12bit RA_i2({4'b0,sum0},sum1,1'b0,sum2,carry2); assign prod = {sum2,mult0[3:0]}; endmodule 4x4 Vedic Multiplier using Ripple carry adder and 2x2 multiplier module vedic4x4( input [3:0] a,b,  output [7:0] prod ); wire [3:0] mult0, mult1, mult2, mult3; wire [3:0] sum0; wire [5:0] sum1, sum2; wire carry0, carry1, carry2; vedic2x2 VM_i0(a[1:0],b[1:0],mult0); vedic2x2 VM_i1(a[1:0],b[3:2],mult1); ...

`timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// // Company: Weekendvlsi.blogspot.com // Engineer: Weekendvlsi //  // Create Date: 27-11-2021 // Design Name:  // Module Name:  // Project Name: Printing nth Fibonacci // Target Devices:  // Tool Versions:  // Description:  //  // Dependencies:  //  // Revision: // Revision 0.01 - File Created // Additional Comments: //  ////////////////////////////////////////////////////////////////////////////////// module nth_fibonacci_num( input clk,  input rst,   input [7:0] nth_fibonacci_req, output [19:0] nth_fibonacci_value     ) ;  reg [19:0] previous_value, present_value;     reg [7:0] ctr;     reg output_valid;  assign nth_fibonacci_value = present_value ; always @( posedge clk) begin         if (rst) begin             previous_value...

  Prime Number Detection: `timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// // Company: Weekendvlsi.blogspot.com // Engineer: Weekendvlsi // Create Date: 27-11-2021 // Design Name: Prime Number Detection // Module Name: prime_number // Project Name:  // Target Devices:  // Tool Versions:  // Description:  // Dependencies:  // Revision: // Revision 0.01 - File Created // Additional Comments: //  ////////////////////////////////////////////////////////////////////////////////// module prime_number ( input clk,  reset) ;   parameter N =50;          // size of array   reg [31:0] dump[0:N-1]; // memory array for product          integer i=0 ;                  integer result_done =1;        integer count =0;        always @(posedge clk )   ...

  FIFO (First In and First Out): `timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// // Company: www.weekendVLSI.blogspot.com // Engineer:  www.weekendVLSI.blogspot.com     // Design Name:    FIFO // Module Name:    fifo_verilog  // Project Name:    FIFO ////////////////////////////////////////////////////////////////////////////////// module fifo_verilog(     input rst,     input clk,     input wr_en,     input rd_en,     input [7:0] wr_data,     output [7:0] rd_data,     output Memory_full,     output Memory_empty     ); reg [7:0]Memory_temp[15:0]; integer wr_index, rd_index; integer r_fifo_count = 0; wire w_full, w_empty; always @(posedge(clk)) begin   if (rst == 1) begin      wr_index=1'b0;   rd_index=1'b0;   r_fifo_count=0;    end ...

 Rising Edge Detector: `timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// // Company: Weekendvlsi.blogspot.com // Engineer: Weekendvlsi // Create Date:  // Design Name: Rising Edge Detector // Module Name: pos_detect ////////////////////////////////////////////////////////////////////////////////// module pos_detect (output neg_det, input clk,rst,d);   reg  q,y;  always @(posedge clk  ) begin      if(rst)         q<=0;     else begin         q<=d;      end    end   not v1 (y,q);    and v2 (neg_det,y,d);  endmodule  RESULTS :                        

 Falling Edge Detector : `timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// // Company: Weekendvlsi.blogspot.com // Engineer: Weekendvlsi // Create Date:  // Design Name: Falling Edge Detector  // Module Name: neg_detect  ////////////////////////////////////////////////////////////////////////////////// module neg_detect (output neg_det, input clk,rst,d);   reg  q,y;    always @(posedge clk  ) begin      if(rst)         q<=0;     else begin         q<=d;     end    end   not v1 (y,d);     and v2 (neg_det,y,q);   endmodule  Result:

Method -1: module clk_divider ( input clk,rst, input [2:0] a, output reg f2,f4,f8,f16,f32,f64,f128 ); reg [6:0] q; always@(posedge clk, posedge rst) begin   if(rst)    f2=1'b0;    else begin     q[0]=~f2; if(a==3'b001) f2=q[0]; else f2=1'b0; end end always@(posedge q[0], posedge rst) begin   if(rst)    f4=1'b0;    else begin     q[1]=~f4; if(a==3'b010) f4=q[1]; else f4=1'b0; end end always@(posedge q[1], posedge rst) begin   if(rst)    f8=1'b0;    else begin     q[2]=~f8; if(a==3'b011) f8=q[2]; else f8=1'b0; end end always@(posedge q[2], posedge rst) begin   if(rst)    f16=1'b0;    else begin     q[3]=~f16; if(a==3'b100) f16=q[3]; else f16=1'b0; end end always@(posedge q[3], posedge rst) begin   if(rst)    f32=1'b0;    else begin     q[4]=~f32; if(a==...

  4X4 BOOTH MULTIPLIER module BOOTH_Multiplier(RESULT, X, Y);   RESULT reg signed [7:0] RESULT;   input signed [3:0] X,Y;  reg [1:0] State;   reg [5:0] K;   reg e;   reg [3:0] Z;   always @(X,Y)   begin     RESULT = 8'd0;     e = 1'b0;     Z = -Y;          for (K=0; K<4; K=K+1)     begin       State = { X[K], e };       case(State)         2'd2 : RESULT[7:4] = RESULT[7:4] + Z;         2'd1 : RESULT[7:4] = RESULT[7:4] + Y;       endcase       RESULT = RESULT >> 1;       RESULT[7] = RESULT[6];       e=X[K];            end   end    endmodule

  Vending machine Top Module : module vending_machine_top (input                 clk,                                                     input                  rst,            input                  coin_valid,            input [2:0]         coin,            output                 cup_f,            output [375:0]   Display_out,           output  [5:0]      bal                           ...

 1bit Subtractor : module full_sub_bit(Diff,Bout,A,B,BI); output Diff,Bout; input  A,B,BI;    wire x,x1,y,z,y2;   xor V1 (x,A,B),V2 (Diff,x,BI);     not V3 (y,A),v4 (x1,x);   and V5 (z,y,B),V6 (y2,x1,BI);   or   V7 (Bout,y2,z);  endmodule 3bit Subtractor : module full_sub_3bit (Sub, BO, A, B, BI,);   input [2:0] A, B;   input BI;   output [2:0] Sub;   output BO;   wire B1,B2;   full_sub_bit v1 (Sub[0],B1,A[0],B[0],BI);    (Module name  Instantiation name   Ports mapping);    full_sub_bit v2 (Sub[1],B2,A[1],B[1],B1);    full_sub_bit v3 (Sub[2],BO,A[2],B[2],B2);   endmodule  TESTBENCH module tb;   reg  [2:0] A,B;   reg  BI;     wire [2:0] Sub;   wire BO;     full_sub_3bit dut  (Sub, BO, A, B, BI,);      initial begin         A=3'b000; B=3'b10...