Number of one's Detection in Input - Verilog Implementation
Number of one's Detection: `timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// // Company: Weekendvlsi.blogspot.com // Engineer: Weekendvlsi // Create Date: 20-11-2021 // Design Name: Number of one's Detection // Module Name: num_ones ////////////////////////////////////////////////////////////////////////////////// module num_ones( input [15:0] In, output reg [5:0] ones_detect ); integer i; always@(In) begin ones_detect= 0; for(i=0;i<16;i=i+1) begin if(In[i] == 1'b1) ones_detect = ones_detect + 1; end end endmodule TEST BENCH: module tb; reg [15:0] In; wire [5:0] ones_detect; num_ones dut ( In,ones_detect); initial begin In...