Posts

Showing posts with the label Sequence Detector

101101 Sequence Detector

Image
Code for detecting pattern from the Seq_in input. `timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// // Company: Weekendvlsi.blogspot.com // Engineer: Weekendvlsi //  // Create Date: 20-11-2021 // Design Name:  // Module Name: pattern_detector // Project Name:  // Target Devices:  // Tool Versions:  // Description:  //  // Dependencies:  //  // Revision: // Revision 0.01 - File Created // Additional Comments: //  ////////////////////////////////////////////////////////////////////////////////// module pattern_detector(rst,clk,seq_in,pattern_detected); output reg pattern_detected;   input clk, rst, seq_in; reg [2:0] current_state; reg [2:0] next_state; parameter [2:0] state_0=3'b000; parameter [2:0] state_1=3'b001; parameter [2:0] state_2=3'b010; parameter [2:0] state_3=3'b011; parameter [2:0] state_4=3'b100; parameter [2:0] state_5=3'b101; always @(p...