101101 Sequence Detector

-

Code for detecting pattern from the Seq_in input.


`timescale 1ns / 1ps

//////////////////////////////////////////////////////////////////////////////////

// Company: Weekendvlsi.blogspot.com

// Engineer: Weekendvlsi

// 

// Create Date: 20-11-2021

// Design Name: 

// Module Name: pattern_detector

// Project Name: 

// Target Devices: 

// Tool Versions: 

// Description: 

// 

// Dependencies: 

// 

// Revision:

// Revision 0.01 - File Created

// Additional Comments:

// 

//////////////////////////////////////////////////////////////////////////////////


module pattern_detector(rst,clk,seq_in,pattern_detected);


output reg pattern_detected;

  input clk, rst, seq_in;


reg [2:0] current_state;

reg [2:0] next_state;


parameter [2:0] state_0=3'b000;

parameter [2:0] state_1=3'b001;

parameter [2:0] state_2=3'b010;

parameter [2:0] state_3=3'b011;

parameter [2:0] state_4=3'b100;

parameter [2:0] state_5=3'b101;


always @(posedge clk, posedge rst) begin

if (rst)

    current_state <= state_0;

  else

    current_state <= next_state;

end


always @(*) begin

   next_state = current_state ;

case(current_state)

state_0:

if (seq_in) begin

    next_state=state_1;

    pattern_detected=1'b0;

    end

    else begin

    next_state=state_0;

    pattern_detected=1'b0;

    end

  

  state_1:

    if (seq_in) begin

    next_state=state_1;

    pattern_detected=1'b0;

    end

    else begin

    next_state=state_2;

    pattern_detected=1'b0;

    end


  state_2:

    if (seq_in) begin

    next_state=state_3;

    pattern_detected=1'b0;

    end

    else begin

    next_state=state_0;

    pattern_detected=1'b0;

    end

  

  state_3:

    if (seq_in) begin

    next_state=state_4;

    pattern_detected=1'b0;

    end

    else begin

    next_state=state_2;

    pattern_detected=1'b0;

    end


  state_4:

    if (seq_in) begin 

    next_state=state_1;

    pattern_detected=1'b0;

    end

    else begin

    next_state=state_5;

    pattern_detected=1'b0;

    end

  

  state_5:

    if (seq_in) begin

    next_state=state_1;

    pattern_detected=1'b1;

    end

    else begin

    next_state=state_0;

    pattern_detected=1'b0;

    end


  default:

    begin

            next_state=state_0;

            pattern_detected=1'b0;

    end

  endcase

  end

endmodule


Comments

Post a Comment

Popular posts from this blog

Weekend VLSI HOME

-
    Weekend VLSI   About Us :  Struggling a lot to enter into the VLSI Industry? We too went through this phase, Trust us and do work hard. If we can get into Industry, YOU TOO CAN . To help you, we come up with this blog. It's in initial phase, We'll keep gathering information and place it in front of you in Simple terms. Also give use some feedbacks or the topics you are interested and want to know further, We'll post on that as well.  VLSI COMPANIES LIST RTL CODING GUIDE LINES RTL coding Guide Lines DIGTIAL ELECTRONICS QUESTIONS   Digital Electronics Questions   RTL DESIGN QUESTIONS RTL Design Questions RTL CODING EXAMPLES Vending Machine With Display options Different ways to Design ROM   6 bit Full adder Using 3 bit Full adder   3 bit Subtractor  Post Divider 4x4 Booth Multiplier 101101 Sequence Detector Falling Edge Detector Rising Edge Detector FIFO Number of one's Detection In Input Prime Number Fibonacci Number 8x8 Vedic Multiplier Rational Clock Division   Di
Read more

Digital Electronics Questions For VLSI Interview

-
Digital Electronics Questions For VLSI Interview   Which gates are called universal gates? Why? Define: (a) bit (b) nibble (c) byte (d) word What is weighted code? Give example.  Give an example for Non-weighted code .  What is the key feature of Excess-3 code? What is the condition for a weighted code to be self-complementary? Convert the binary number 011101010001 to octal and hexadecimal?How many number of 2 input AND gates are required to generate N I/P AND gate? State De-Morgan’s Laws? If it is given that A & B will not be 1 at the same time, what will be theequivalent logical gate for an XOR gate?  If any of the inputs of an XOR gate are inverted, XOR gate will work as ----- ? Give implementation of XOR using minimum number of NAND gates? Which logical gates can be used as parity generators? Which logical gate can be used to find out whether the two single bit inputs are equal or not?  What is the difference between NAND gate and negative AND gate? XOR gate can be used as eve
Read more

stratified event queue in Verilog

-
Image
  stratified event queue in Verilog  1) Active Region  :    Events which occur at the current simulation time and can be executed in any order. These include blocking assignments, continuous assignments, $display commands, evaluation of instance and primitive inputs followed by updates of primitive and instance outputs, and the evaluation of nonblocking RHS expressions. Ex : a=b; 2) Inactive Region:    Events which are processed after the processing of active events. In this queue, #0 delay assignments have been scheduled. Ex : a= #0 b; 3) Nonblocking Region:    Events evaluated during previous simulation time but are assigned at this simulation time after the processing of active and inactive events. It is in this queue where the LHS of nonblocking assignment is updated. Ex : a <=b; 4) Postpone Region:   Events that are processed after all the active, inactive, and nonblocking assigned update events have been processed. This queue contains $monitor and $strobe assignments.
Read more