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stratified event queue in Verilog

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  stratified event queue in Verilog  1) Active Region  :    Events which occur at the current simulation time and can be executed in any order. These include blocking assignments, continuous assignments, $display commands, evaluation of instance and primitive inputs followed by updates of primitive and instance outputs, and the evaluation of nonblocking RHS expressions. Ex : a=b; 2) Inactive Region:    Events which are processed after the processing of active events. In this queue, #0 delay assignments have been scheduled. Ex : a= #0 b; 3) Nonblocking Region:    Events evaluated during previous simulation time but are assigned at this simulation time after the processing of active and inactive events. It is in this queue where the LHS of nonblocking assignment is updated. Ex : a <=b; 4) Postpone Region:   Events that are processed after all the active, inactive, and nonblocking assigned update events have been processed. This que...

Different ways to design 8X3 Priority Encoder

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  module Priority_8_3 (y2,y1,y0,a,b,c,d,e,f,g,h); input a,b,c,d,e,f,g,h; output reg y2,y1,y0; `ifdef method1 always @* begin     case ({a,b,c,d,e,f,g,h}) 8'b11111111: {y2,y1,y0} =3'b111; 8'b11111110: {y2,y1,y0} =3'b111; 8'b11111101: {y2,y1,y0} =3'b111; 8'b11111100: {y2,y1,y0} =3'b111; 8'b11111011: {y2,y1,y0} =3'b111; 8'b11111010: {y2,y1,y0} =3'b111; 8'b11111001: {y2,y1,y0} =3'b111; 8'b11111000: {y2,y1,y0} =3'b111; 8'b11110111: {y2,y1,y0} =3'b111; 8'b11110110: {y2,y1,y0} =3'b111; 8'b11110101: {y2,y1,y0} =3'b111; 8'b11110100: {y2,y1,y0} =3'b111; 8'b11110011: {y2,y1,y0} =3'b111; 8'b11110010: {y2,y1,y0} =3'b111; 8'b11110001: {y2,y1,y0} =3'b111; 8'b11110000: {y2,y1,y0} =3'b111; 8'b11101111: {y2,y1,y0} =3'b111; 8'b11101110: {y2,y1,y0} =3'b111; 8'b11101101: {y2,y1,y0} =3'b111; 8'b11101100: {y2,y1,y0} =3'b111; 8'b11101011: {y2,y1,...

Digital Electronics Questions For VLSI Interview

Digital Electronics Questions For VLSI Interview   Which gates are called universal gates? Why? Define: (a) bit (b) nibble (c) byte (d) word What is weighted code? Give example.  Give an example for Non-weighted code .  What is the key feature of Excess-3 code? What is the condition for a weighted code to be self-complementary? Convert the binary number 011101010001 to octal and hexadecimal?How many number of 2 input AND gates are required to generate N I/P AND gate? State De-Morgan’s Laws? If it is given that A & B will not be 1 at the same time, what will be theequivalent logical gate for an XOR gate?  If any of the inputs of an XOR gate are inverted, XOR gate will work as ----- ? Give implementation of XOR using minimum number of NAND gates? Which logical gates can be used as parity generators? Which logical gate can be used to find out whether the two single bit inputs are equal or not?  What is the difference between NAND gate and negative AND gate? XOR...