FIFO Design Using Verilog HDL
FIFO (First In and First Out): `timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// // Company: www.weekendVLSI.blogspot.com // Engineer: www.weekendVLSI.blogspot.com // Design Name: FIFO // Module Name: fifo_verilog // Project Name: FIFO ////////////////////////////////////////////////////////////////////////////////// module fifo_verilog( input rst, input clk, input wr_en, input rd_en, input [7:0] wr_data, output [7:0] rd_data, output Memory_full, output Memory_empty ); reg [7:0]Memory_temp[15:0]; integer wr_index, rd_index; integer r_fifo_count = 0; wire w_full, w_empty; always @(posedge(clk)) begin if (rst == 1) begin wr_index=1'b0; rd_index=1'b0; r_fifo_count=0; end ...