FIFO Design Using Verilog HDL
FIFO (First In and First Out):
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: www.weekendVLSI.blogspot.com
// Engineer: www.weekendVLSI.blogspot.com
// Design Name: FIFO
// Module Name: fifo_verilog
// Project Name: FIFO
//////////////////////////////////////////////////////////////////////////////////
module fifo_verilog(
input rst,
input clk,
input wr_en,
input rd_en,
input [7:0] wr_data,
output [7:0] rd_data,
output Memory_full,
output Memory_empty
);
reg [7:0]Memory_temp[15:0];
integer wr_index, rd_index;
integer r_fifo_count = 0;
wire w_full, w_empty;
always @(posedge(clk)) begin
if (rst == 1) begin
wr_index=1'b0;
rd_index=1'b0;
r_fifo_count=0;
end
else begin
if (wr_en == 1'b1 && rd_en == 1'b0 && r_fifo_count < 16) begin
r_fifo_count <= r_fifo_count + 1;
end
else if (wr_en == 1'b0 && rd_en == 1'b1 && r_fifo_count > 0) begin
r_fifo_count <= r_fifo_count - 1;
end
if (wr_en == 1'b1 && w_full == 1'b0) begin
if (wr_index == 15) begin
wr_index <= 1'b0;
end
else begin
wr_index <= wr_index + 1;
end
end
end
if (rd_en == 1'b1 && w_empty == 1'b0) begin
if (rd_index == 15) begin
rd_index <= 1'b0;
end
else begin
rd_index <= rd_index + 1;
end
end
if (wr_en == 1'b1 && w_full == 1'b0) begin
Memory_temp[wr_index] <= wr_data;
end
end
assign rd_data = Memory_temp[rd_index];
assign w_full = (r_fifo_count == 16)? 1'b1 : 1'b0;
assign w_empty = (r_fifo_count == 0)? 1'b1 : 1'b0;
assign Memory_full = w_full;
assign Memory_empty = w_empty;
endmodule
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