Vedic Multiplier Design

-

8x8 Vedic Multiplier using Ripple carry adder and 4x4 multiplier

module vedic8x8(
input [7:0] a,b, 
output [15:0] prod
);

wire [7:0] mult0, mult1, mult2, mult3;
wire [7:0] sum0;
wire [11:0] sum1, sum2;
wire carry0, carry2, carry3;

vedic4x4 VM_i0(a[3:0],b[3:0],mult0);
vedic4x4 VM_i1(a[3:0],b[7:4],mult1);
vedic4x4 VM_i2(a[7:4],b[3:0],mult2);
vedic4x4 VM_i3(a[7:4],b[7:4],mult3);

ripple_adder_8bit RA_i0({4'b0,mult0[7:4]},mult2,1'b0,sum0,carry0);
ripple_adder_12bit RA_i1({4'b0,mult1},{mult3,4'b0},1'b0,sum1,carry1);
ripple_adder_12bit RA_i2({4'b0,sum0},sum1,1'b0,sum2,carry2);

assign prod = {sum2,mult0[3:0]};

endmodule

4x4 Vedic Multiplier using Ripple carry adder and 2x2 multiplier
module vedic4x4(
input [3:0] a,b, 
output [7:0] prod
);

wire [3:0] mult0, mult1, mult2, mult3;
wire [3:0] sum0;
wire [5:0] sum1, sum2;
wire carry0, carry1, carry2;

vedic2x2 VM_i0(a[1:0],b[1:0],mult0);
vedic2x2 VM_i1(a[1:0],b[3:2],mult1);
vedic2x2 VM_i2(a[3:2],b[1:0],mult2);
vedic2x2 VM_i3(a[3:2],b[3:2],mult3);

ripple_adder_4bit RA_i0({2'b0,mult0[3:2]},mult2,1'b0,sum0,carry0);
ripple_adder_6bit RA_i1({2'b0,mult1},{mult3,2'b0},1'b0,sum1,carry1);
ripple_adder_6bit RA_i2({2'b0,sum0},sum1,1'b0,sum2,carry2);
assign prod = {sum2,mult0[1:0]};

endmodule


2X2 Vedic Multiplier using Half Adders
module vedic2x2(
input [1:0] a,b, 
output [3:0] prod
);

wire a1b1 = a[1] & b[1];
wire a0b1 = a[0] & b[1];
wire a1b0 = a[1] & b[0];
wire a0b0 = a[0] & b[0];
wire carry;
assign prod[0] = a0b0;

half_adder HA_i0(a0b1,a1b0,prod[1],carry);
half_adder HA_i1(a1b1,carry,prod[2],prod[3]);

endmodule

12 bit Ripple Carry Adder using 6bit Ripple carry Adder
module ripple_adder_12bit(
input [11:0] a,b, 
input cin, 
output [11:0] sum, 
output cout
);

wire carry;

ripple_adder_6bit RA_i0(a[5:0],b[5:0],cin,sum[5:0],carry);
ripple_adder_6bit RA_i1(a[11:6],b[11:6],carry,sum[11:6],cout);

endmodule

8 bit Ripple Carry Adder using 4bit Ripple carry Adder
module ripple_adder_8bit(
input [7:0] a,b, 
input cin, 
output [7:0] sum, 
output cout
);

wire carry;

ripple_adder_4bit RA_i0(a[3:0],b[3:0],cin,sum[3:0],carry);
ripple_adder_4bit RA_i1(a[7:4],b[7:4],carry,sum[7:4],cout);

endmodule
6 bit Ripple Carry Adder using Full Adders
module ripple_adder_4bit(
input [3:0] a,b, 
input cin, 
output [3:0] sum, 
output cout
);

wire carry1, carry2, carry3;
full_adder FA_i0(a[0],b[0],cin,sum[0],carry1);
full_adder FA_i1(a[1],b[1],carry1,sum[1],carry2);
full_adder FA_i2(a[2],b[2],carry2,sum[2],carry3);
full_adder FA_i3(a[3],b[3],carry3,sum[3],cout);

endmodule

4 bit Ripple Carry Adder using Full adder
module ripple_adder_4bit(
input [3:0] a,b, 
input cin, 
output [3:0] sum, 
output cout
);

wire carry1, carry2, carry3;
full_adder FA_i0(a[0],b[0],cin,sum[0],carry1);
full_adder FA_i1(a[1],b[1],carry1,sum[1],carry2);
full_adder FA_i2(a[2],b[2],carry2,sum[2],carry3);
full_adder FA_i3(a[3],b[3],carry3,sum[3],cout);

endmodule

Full Adder usinf Half Adder

module full_adder(input a, b, cin, output sum, cout);

wire sum1,carry1,carry2;
half_adder HA0(a,b,sum1,carry1);
half_adder HA1(cin,sum1,sum,carry2);

assign cout = carry1 | carry2;

endmodule

Half Adder 

module half_adder(

input a,b, 

output sum, carry

);

assign sum = a ^ b;

assign carry = a & b;

endmodule






Comments

Post a Comment

Popular posts from this blog

Weekend VLSI HOME

-
    Weekend VLSI   About Us :  Struggling a lot to enter into the VLSI Industry? We too went through this phase, Trust us and do work hard. If we can get into Industry, YOU TOO CAN . To help you, we come up with this blog. It's in initial phase, We'll keep gathering information and place it in front of you in Simple terms. Also give use some feedbacks or the topics you are interested and want to know further, We'll post on that as well.  VLSI COMPANIES LIST RTL CODING GUIDE LINES RTL coding Guide Lines DIGTIAL ELECTRONICS QUESTIONS   Digital Electronics Questions   RTL DESIGN QUESTIONS RTL Design Questions RTL CODING EXAMPLES Vending Machine With Display options Different ways to Design ROM   6 bit Full adder Using 3 bit Full adder   3 bit Subtractor  Post Divider 4x4 Booth Multiplier 101101 Sequence Detector Falling Edge Detector Rising Edge Detector FIFO Number of one's Detection In Input Prime Number Fibonacci Number 8x8 Vedic M...
Read more

Digital Electronics Questions For VLSI Interview

-
Digital Electronics Questions For VLSI Interview   Which gates are called universal gates? Why? Define: (a) bit (b) nibble (c) byte (d) word What is weighted code? Give example.  Give an example for Non-weighted code .  What is the key feature of Excess-3 code? What is the condition for a weighted code to be self-complementary? Convert the binary number 011101010001 to octal and hexadecimal?How many number of 2 input AND gates are required to generate N I/P AND gate? State De-Morgan’s Laws? If it is given that A & B will not be 1 at the same time, what will be theequivalent logical gate for an XOR gate?  If any of the inputs of an XOR gate are inverted, XOR gate will work as ----- ? Give implementation of XOR using minimum number of NAND gates? Which logical gates can be used as parity generators? Which logical gate can be used to find out whether the two single bit inputs are equal or not?  What is the difference between NAND gate and negative AND gate? XOR...
Read more

stratified event queue in Verilog

-
Image
  stratified event queue in Verilog  1) Active Region  :    Events which occur at the current simulation time and can be executed in any order. These include blocking assignments, continuous assignments, $display commands, evaluation of instance and primitive inputs followed by updates of primitive and instance outputs, and the evaluation of nonblocking RHS expressions. Ex : a=b; 2) Inactive Region:    Events which are processed after the processing of active events. In this queue, #0 delay assignments have been scheduled. Ex : a= #0 b; 3) Nonblocking Region:    Events evaluated during previous simulation time but are assigned at this simulation time after the processing of active and inactive events. It is in this queue where the LHS of nonblocking assignment is updated. Ex : a <=b; 4) Postpone Region:   Events that are processed after all the active, inactive, and nonblocking assigned update events have been processed. This que...
Read more