Weekend VLSI

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  module Priority_8_3 (y2,y1,y0,a,b,c,d,e,f,g,h); input a,b,c,d,e,f,g,h; output reg y2,y1,y0; `ifdef method1 always @* begin     case ({a,b,c,d,e,f,g,h}) 8'b11111111: {y2,y1,y0} =3'b111; 8'b11111110: {y2,y1,y0} =3'b111; 8'b11111101: {y2,y1,y0} =3'b111; 8'b11111100: {y2,y1,y0} =3'b111; 8'b11111011: {y2,y1,y0} =3'b111; 8'b11111010: {y2,y1,y0} =3'b111; 8'b11111001: {y2,y1,y0} =3'b111; 8'b11111000: {y2,y1,y0} =3'b111; 8'b11110111: {y2,y1,y0} =3'b111; 8'b11110110: {y2,y1,y0} =3'b111; 8'b11110101: {y2,y1,y0} =3'b111; 8'b11110100: {y2,y1,y0} =3'b111; 8'b11110011: {y2,y1,y0} =3'b111; 8'b11110010: {y2,y1,y0} =3'b111; 8'b11110001: {y2,y1,y0} =3'b111; 8'b11110000: {y2,y1,y0} =3'b111; 8'b11101111: {y2,y1,y0} =3'b111; 8'b11101110: {y2,y1,y0} =3'b111; 8'b11101101: {y2,y1,y0} =3'b111; 8'b11101100: {y2,y1,y0} =3'b111; 8'b11101011: {y2,y1,...

Module : `timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// // Company: Weekendvlsi.blogspot.com // Engineer: Weekendvlsi // Create Date:  // Design Name: Rational clock divider - Division by 4.5  // Module Name:  clk_div // Project Name:  // Target Devices:  // Tool Versions:  // Description:  // Dependencies:  // Revision: // Revision 0.01 - File Created // Additional Comments: //  ////////////////////////////////////////////////////////////////////////////////// module clk_div (clk,rst,clk_4_5);   input clk; input rst; output clk_4_5;   reg [8:0]  count;   reg  SATcount1,SATcount5,SATcount6 ;    /* Counter rst value : 9?b000000001 */ /* count is a  ring counter */   always @( posedge clk or posedge rst) if (rst) count <='d1; else begin count <= count << 1; count[0] <= count[8]; end always @(negedge clk or posedge rst) ...

8x8 Vedic Multiplier using Ripple carry adder and 4x4 multiplier module vedic8x8( input [7:0] a,b,  output [15:0] prod ); wire [7:0] mult0, mult1, mult2, mult3; wire [7:0] sum0; wire [11:0] sum1, sum2; wire carry0, carry2, carry3; vedic4x4 VM_i0(a[3:0],b[3:0],mult0); vedic4x4 VM_i1(a[3:0],b[7:4],mult1); vedic4x4 VM_i2(a[7:4],b[3:0],mult2); vedic4x4 VM_i3(a[7:4],b[7:4],mult3); ripple_adder_8bit RA_i0({4'b0,mult0[7:4]},mult2,1'b0,sum0,carry0); ripple_adder_12bit RA_i1({4'b0,mult1},{mult3,4'b0},1'b0,sum1,carry1); ripple_adder_12bit RA_i2({4'b0,sum0},sum1,1'b0,sum2,carry2); assign prod = {sum2,mult0[3:0]}; endmodule 4x4 Vedic Multiplier using Ripple carry adder and 2x2 multiplier module vedic4x4( input [3:0] a,b,  output [7:0] prod ); wire [3:0] mult0, mult1, mult2, mult3; wire [3:0] sum0; wire [5:0] sum1, sum2; wire carry0, carry1, carry2; vedic2x2 VM_i0(a[1:0],b[1:0],mult0); vedic2x2 VM_i1(a[1:0],b[3:2],mult1); ...