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ASIC and FPGA Flow Synopsis

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- December 28, 2021

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stratified event queue in Verilog

- February 26, 2022

stratified event queue in Verilog 1) Active Region : Events which occur at the current simulation time and can be executed in any order. These include blocking assignments, continuous assignments, $display commands, evaluation of instance and primitive inputs followed by updates of primitive and instance outputs, and the evaluation of nonblocking RHS expressions. Ex : a=b; 2) Inactive Region: Events which are processed after the processing of active events. In this queue, #0 delay assignments have been scheduled. Ex : a= #0 b; 3) Nonblocking Region: Events evaluated during previous simulation time but are assigned at this simulation time after the processing of active and inactive events. It is in this queue where the LHS of nonblocking assignment is updated. Ex : a <=b; 4) Postpone Region: Events that are processed after all the active, inactive, and nonblocking assigned update events have been processed. This que...

Vending machine Code With Display Options

- November 19, 2021

Vending machine Top Module : module vending_machine_top (input clk, input rst, input coin_valid, input [2:0] coin, output cup_f, output [375:0] Display_out, output [5:0] bal ...

Weekend VLSI HOME

- November 21, 2021

Weekend VLSI About Us : Struggling a lot to enter into the VLSI Industry? We too went through this phase, Trust us and do work hard. If we can get into Industry, YOU TOO CAN . To help you, we come up with this blog. It's in initial phase, We'll keep gathering information and place it in front of you in Simple terms. Also give use some feedbacks or the topics you are interested and want to know further, We'll post on that as well. VLSI COMPANIES LIST RTL CODING GUIDE LINES RTL coding Guide Lines DIGTIAL ELECTRONICS QUESTIONS Digital Electronics Questions RTL DESIGN QUESTIONS RTL Design Questions RTL CODING EXAMPLES Vending Machine With Display options Different ways to Design ROM 6 bit Full adder Using 3 bit Full adder 3 bit Subtractor Post Divider 4x4 Booth Multiplier 101101 Sequence Detector Falling Edge Detector Rising Edge Detector FIFO Number of one's Detection In Input Prime Number Fibonacci Number 8x8 Vedic M...

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$readmemb example
$readmemh example
8X3 Priority Encoder
Booth Multiplier Verilog code
careers in vlsi
Coffee Vending Machine Verilog code
Digital Electronics Questions
Edge Detector Verilog code
Falling Edge Detector Verilog code
Fibonacci number

FIFO RTL code
FIFO Verilog Code.
Full Adder design Using Verilog
Full Adder design Using Verilog HDL
Full Adder RTL design
Milk Vending Machine Verilog code
Number of one's Detection Using Verilog HDL
Pattern Detector
Post Divider
Post Divider RTL code
Prime Number Detection
Ripple carry adder
Rising Edge Dector verilog code
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ROM Design Using assign Statement
ROM Design Using Case Statement
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ROM Memory design in Verilog
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Sequence Detector
Subtractor RTL design
Subtractor design using Verilog HDL
Tea Vending Machine Verilog code
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Vending Machine Verilog code
Verilog 1 bit Subtractor
Verilog 3bit Subtractor
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