Different Ways To Design ROM Verilog HDL

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 ROM is an acronym for Read-Only Memory. It refers to computer memory chips containing permanent or semi-permanent data. ROM is non-volatile; even after you turn off your computer, the contents of ROM will remain. You may see In any ASIC and FPGA designs.





Combinational Block

module ROM_code(data, addr, Enable); parameter width=16; output reg [width-1:0] data; input[3:0] addr; input Enable; reg [width-1:0] ROM[width-1:0]; always @(Enable) begin ROM[0] =16'h2000; ROM[1] =16'h2001; ROM[2] =16'h2002; ROM[3] =16'h2003; ROM[4] =16'h2004;; ROM[5] =16'h2051; ROM[6] =16'h2301; ROM[7] =16'h2061; ROM[8] =16'h9001; ROM[9] =16'h2201; ROM[10]=16'h1001; ROM[11]=16'h2101; ROM[12]=16'h2901; ROM[13]=16'h2050; ROM[14]=16'h2301; ROM[15]=16'h2071; Data=ROM[addr]; end endmodule


Sequential Logic


module ROM_code(data, addr, clk); parameter width=16; output reg [width-1:0] data; input[3:0] addr; input clk; reg [width-1:0] ROM[width-1:0]; always @(posedge clk) begin ROM[0] <=16'h2000; ROM[1] <=16'h2001; ROM[2] <=16'h2002; ROM[3] <=16'h2003; ROM[4] <=16'h2004;; ROM[5] <=16'h2051; ROM[6] <=16'h2301; ROM[7] <=16'h2061; ROM[8] <=16'h9001; ROM[9] <=16'h2201; ROM[10]<=16'h1001; ROM[11]<=16'h2101; ROM[12]<=16'h2901; ROM[13]<=16'h2050; ROM[14]<=16'h2301; ROM[15]<=16'h2071; Data<=ROM[addr]; end endmodule



$readmemb


module ROM_code(data, addr, clk); parameter width=8; output reg [width-1:0] data; input[3:0] addr; input clk; reg [width-1:0] ROM[width-1:0]; initial $readmemb("Mem.mem", ROM); always @(posedge clk) begin data=ROM[addr]; end endmodule


In Design we need to create Memory file then its saved with .mem extension .
Above Memory file name is Mem so It saved as Mem.mem.






We can use $readmemh also, for that you need to give Hexadecimal values in Memory file.


Case Statement


module ROM_code(data, addr); parameter width=16; output [width-1:0] data; input[2:0] addr; always@(addr) begin case(addr) 'd0: data=16'd1; 'd1: data=16'd2; 'd2: data=16'd3; 'd3: data=16'd4; 'd4: data=16'd5; 'd5: data=16'd6; 'd6: data=16'd7; 'd7: data=16'd8; default: data=16'd0; endcase end endmodule


assign


module ROM_code(data, addr, Enable); parameter width=16; output [width-1:0] data; input[3:0] addr; input Enable; reg [width-1:0] ROM[6:0]; always @(Enable) begin ROM[0] =16'h2000; ROM[1] =16'h2001; ROM[2] =16'h2002; ROM[3] =16'h2003; ROM[4] =16'h2004;; ROM[5] =16'h2051; ROM[6] =16'h2301; end assign Data=ROM[addr]; endmodule





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