ASIC and FPGA Flow Synopsis
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Different ways to design 8X3 Priority Encoder
module Priority_8_3 (y2,y1,y0,a,b,c,d,e,f,g,h); input a,b,c,d,e,f,g,h; output reg y2,y1,y0; `ifdef method1 always @* begin case ({a,b,c,d,e,f,g,h}) 8'b11111111: {y2,y1,y0} =3'b111; 8'b11111110: {y2,y1,y0} =3'b111; 8'b11111101: {y2,y1,y0} =3'b111; 8'b11111100: {y2,y1,y0} =3'b111; 8'b11111011: {y2,y1,y0} =3'b111; 8'b11111010: {y2,y1,y0} =3'b111; 8'b11111001: {y2,y1,y0} =3'b111; 8'b11111000: {y2,y1,y0} =3'b111; 8'b11110111: {y2,y1,y0} =3'b111; 8'b11110110: {y2,y1,y0} =3'b111; 8'b11110101: {y2,y1,y0} =3'b111; 8'b11110100: {y2,y1,y0} =3'b111; 8'b11110011: {y2,y1,y0} =3'b111; 8'b11110010: {y2,y1,y0} =3'b111; 8'b11110001: {y2,y1,y0} =3'b111; 8'b11110000: {y2,y1,y0} =3'b111; 8'b11101111: {y2,y1,y0} =3'b111; 8'b11101110: {y2,y1,y0} =3'b111; 8'b11101101: {y2,y1,y0} =3'b111; 8'b11101100: {y2,y1,y0} =3'b111; 8'b11101011: {y2,y1,...
Rational clock divider - Division by 4.5 example
Module : `timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// // Company: Weekendvlsi.blogspot.com // Engineer: Weekendvlsi // Create Date: // Design Name: Rational clock divider - Division by 4.5 // Module Name: clk_div // Project Name: // Target Devices: // Tool Versions: // Description: // Dependencies: // Revision: // Revision 0.01 - File Created // Additional Comments: // ////////////////////////////////////////////////////////////////////////////////// module clk_div (clk,rst,clk_4_5); input clk; input rst; output clk_4_5; reg [8:0] count; reg SATcount1,SATcount5,SATcount6 ; /* Counter rst value : 9?b000000001 */ /* count is a ring counter */ always @( posedge clk or posedge rst) if (rst) count <='d1; else begin count <= count << 1; count[0] <= count[8]; end always @(negedge clk or posedge rst) ...