RTL Guide Lines

Guideline 1 : Need to state all the conditions else un-intentional latches will come up.

Example :

case (x,y)

00,01: z=1;

10: z=0 ; //11 case will infer a latch which isn't required

endcase

Guideline 2 : Perfect synchronization should be maintained for the external world signals coming into the chip.

Guideline 3 : Have a good knowledge on CDC and double check the signals going through multiple clock domains.

Guideline 4 : Don't mix up Blocking and Non Blocking statements in an always block. Always know the differences netween blocking and non blocking assignments.

Guideline 5 : It is always suggested to seperate combinational and sequential logic.

Guideline 6 : Have an idea of where to use reg and where to use wire.

Guideline 7 : To design a synthesizable logic, know the synthesizable keywords and use it properly.

Guideline 8 : The sensitivity list of a combinational always block must include all the inputs used in that block. If you forget some signals from the sensitivity list, synthesis will silently assume they are included and generate gates. However, the Verilog simulator will respect your incomplete sensitivity list and the simulation behavior will be incorrect.

Example 

always @(x or y or z or k) begin

if(cond)

out = x + y;

else

out = z + k;

end

Guideline 9 : To generate actual gates during synthesis, all loops will be unrolled. That also implies that the iterations can be determined once and for all, they can't depend on dynamic values. Loop ranges can be constants, parameters or `define, but not expressions based on signals.

Guideline 10 : You can't drive the same signal from multiple always blocks, it would result in multiple drivers trying to write to the same signal, which is not possible.