RTL Design Interview Questions

-

 

  1. Explain the difference between synchronous and asynchronous FIFO designs and their uses.
  2. Can you design a parameterized 2:1 multiplexer?
  3. Explain the difference between these three versions of Verilog case statement: cases, casez and case-inside. Also, when do you use these as an RTL engineer?
  4. What do you do at the RTL level to meet timing in synthesis? Provide an example.
  5. What's the difference between SRAM and DRAM?
  6. Difference between Latch and Flipflop?
  7. What are two ways of converting a two-input NAND gate to an inverter?
  8. write a code for edge detector ?
  9. Can you tell me about the engineering design process?
  10. Explain how to quickly identify whether a number is a power of 2.
  11. What's a unary operator?
  12. Setup time and Hold Time ?
  13. Design NAND Gate Using 2:1 Mux?
  14. Design Flipflop using Latch?
  15. Difference between Blocking and Non Blocking Statements ?
  16. Explain Parallel and Sequence Statements?
  17. Explain ASIC and FPGA Difference ?
  18. What is Meta Stability?
  19. Design XOR from NAND gates? 
  20. Design XOR from NOR gate?
  21. How to design and FIFO and calculate FIFO depth for rate change implementations?
  22.  Implement 4:1Mux using 2:1 Mux without using any additional gates.
  23.  Implement a full adder using two 4:1 Mux ?
  24.  Design a 16:1 Mux using 2:1 Mux ?
  25.  Implement a 2:1 Mux using Tristate buffers ?
  26.  Implement the following function using 2:1 Mux ?
  27.  Design a full adder using 3:8 Decoder(Both active high and low) ?
  28.  Questions on priority encoder and it's implementation?
  29.  Difference between latch and flip flop ?
  30.  Conversion of one flip to another like JK to SR,T to D etc?
  31.  SISO and PIPO implementation ?
  32. For a counter which one is better for implementation? Johnson Counter, Ring Counter, Ripple counter. ?
  33.  Decade counter and up/down counter implementation ?
  34.  Mod counter with specified duty cycle implementation?
  35.  Sequence Detector like 10101 is given and you are asked to implement this FSM depending on overlapping and non overlapping method(High Priority) ?
  36.  Difference between Mealy and Moore SM?
  37.  Different types of Hazards and their usage? 
  38.  Difference between Setup time and Hold time and explain with waveform?
  39.  Propagation delay and contamination delay?
  40.  Questions on Clock skew, Slack and Slew?  
  41. Which one is more dangerous? Setup time violations or Hold Time violations? Why?
  42. What is the meaning of " inferring latch" ?
  43. What is sensitivity list ?
  44. What is CDC and how you deal with it?
  45. How do you implement asynchronous reset and synchronous reset?
  46. Difference between Task and Function?

Comments

Post a Comment

Popular posts from this blog

Weekend VLSI HOME

-
    Weekend VLSI   About Us :  Struggling a lot to enter into the VLSI Industry? We too went through this phase, Trust us and do work hard. If we can get into Industry, YOU TOO CAN . To help you, we come up with this blog. It's in initial phase, We'll keep gathering information and place it in front of you in Simple terms. Also give use some feedbacks or the topics you are interested and want to know further, We'll post on that as well.  VLSI COMPANIES LIST RTL CODING GUIDE LINES RTL coding Guide Lines DIGTIAL ELECTRONICS QUESTIONS   Digital Electronics Questions   RTL DESIGN QUESTIONS RTL Design Questions RTL CODING EXAMPLES Vending Machine With Display options Different ways to Design ROM   6 bit Full adder Using 3 bit Full adder   3 bit Subtractor  Post Divider 4x4 Booth Multiplier 101101 Sequence Detector Falling Edge Detector Rising Edge Detector FIFO Number of one's Detection In Input Prime Number Fibonacci Number 8x8 Vedic Multiplier Rational Clock Division   Di
Read more

Digital Electronics Questions For VLSI Interview

-
Digital Electronics Questions For VLSI Interview   Which gates are called universal gates? Why? Define: (a) bit (b) nibble (c) byte (d) word What is weighted code? Give example.  Give an example for Non-weighted code .  What is the key feature of Excess-3 code? What is the condition for a weighted code to be self-complementary? Convert the binary number 011101010001 to octal and hexadecimal?How many number of 2 input AND gates are required to generate N I/P AND gate? State De-Morgan’s Laws? If it is given that A & B will not be 1 at the same time, what will be theequivalent logical gate for an XOR gate?  If any of the inputs of an XOR gate are inverted, XOR gate will work as ----- ? Give implementation of XOR using minimum number of NAND gates? Which logical gates can be used as parity generators? Which logical gate can be used to find out whether the two single bit inputs are equal or not?  What is the difference between NAND gate and negative AND gate? XOR gate can be used as eve
Read more

stratified event queue in Verilog

-
Image
  stratified event queue in Verilog  1) Active Region  :    Events which occur at the current simulation time and can be executed in any order. These include blocking assignments, continuous assignments, $display commands, evaluation of instance and primitive inputs followed by updates of primitive and instance outputs, and the evaluation of nonblocking RHS expressions. Ex : a=b; 2) Inactive Region:    Events which are processed after the processing of active events. In this queue, #0 delay assignments have been scheduled. Ex : a= #0 b; 3) Nonblocking Region:    Events evaluated during previous simulation time but are assigned at this simulation time after the processing of active and inactive events. It is in this queue where the LHS of nonblocking assignment is updated. Ex : a <=b; 4) Postpone Region:   Events that are processed after all the active, inactive, and nonblocking assigned update events have been processed. This queue contains $monitor and $strobe assignments.
Read more