RTL Design Interview Questions

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  1. Explain the difference between synchronous and asynchronous FIFO designs and their uses.
  2. Can you design a parameterized 2:1 multiplexer?
  3. Explain the difference between these three versions of Verilog case statement: cases, casez and case-inside. Also, when do you use these as an RTL engineer?
  4. What do you do at the RTL level to meet timing in synthesis? Provide an example.
  5. What's the difference between SRAM and DRAM?
  6. Difference between Latch and Flipflop?
  7. What are two ways of converting a two-input NAND gate to an inverter?
  8. write a code for edge detector ?
  9. Can you tell me about the engineering design process?
  10. Explain how to quickly identify whether a number is a power of 2.
  11. What's a unary operator?
  12. Setup time and Hold Time ?
  13. Design NAND Gate Using 2:1 Mux?
  14. Design Flipflop using Latch?
  15. Difference between Blocking and Non Blocking Statements ?
  16. Explain Parallel and Sequence Statements?
  17. Explain ASIC and FPGA Difference ?
  18. What is Meta Stability?
  19. Design XOR from NAND gates? 
  20. Design XOR from NOR gate?
  21. How to design and FIFO and calculate FIFO depth for rate change implementations?
  22.  Implement 4:1Mux using 2:1 Mux without using any additional gates.
  23.  Implement a full adder using two 4:1 Mux ?
  24.  Design a 16:1 Mux using 2:1 Mux ?
  25.  Implement a 2:1 Mux using Tristate buffers ?
  26.  Implement the following function using 2:1 Mux ?
  27.  Design a full adder using 3:8 Decoder(Both active high and low) ?
  28.  Questions on priority encoder and it's implementation?
  29.  Difference between latch and flip flop ?
  30.  Conversion of one flip to another like JK to SR,T to D etc?
  31.  SISO and PIPO implementation ?
  32. For a counter which one is better for implementation? Johnson Counter, Ring Counter, Ripple counter. ?
  33.  Decade counter and up/down counter implementation ?
  34.  Mod counter with specified duty cycle implementation?
  35.  Sequence Detector like 10101 is given and you are asked to implement this FSM depending on overlapping and non overlapping method(High Priority) ?
  36.  Difference between Mealy and Moore SM?
  37.  Different types of Hazards and their usage? 
  38.  Difference between Setup time and Hold time and explain with waveform?
  39.  Propagation delay and contamination delay?
  40.  Questions on Clock skew, Slack and Slew?  
  41. Which one is more dangerous? Setup time violations or Hold Time violations? Why?
  42. What is the meaning of " inferring latch" ?
  43. What is sensitivity list ?
  44. What is CDC and how you deal with it?
  45. How do you implement asynchronous reset and synchronous reset?
  46. Difference between Task and Function?

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